Refine your search
Collections
Co-Authors
Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Sinha, Akanksha
- Efficient and Optimized Reversible BCD Adder Using DR Gate
Abstract Views :177 |
PDF Views:4
Authors
Affiliations
1 Department of Electronics and Telecommunication, SSTC/SSGI, Bhilai (C.G.), IN
2 Department of Electronics and Instrumentation, SSTC-SSGI, Bhilai, IN
1 Department of Electronics and Telecommunication, SSTC/SSGI, Bhilai (C.G.), IN
2 Department of Electronics and Instrumentation, SSTC-SSGI, Bhilai, IN
Source
Programmable Device Circuits and Systems, Vol 9, No 6 (2017), Pagination: 123-128Abstract
Reversible logic is becoming a most popular field and has vast opportunities such that it has been search that it is applicable in various technological department; such as in CMOS, nanotechnology and optical computing. This create an new effect in area of computation which teaches about computation. Quantum Computing results in operation and function. The reversible arithmetic designs are very effective regarding counting of reversible gates, delay and quantum cost. Design and timing constraint of all adders results in efficient processing. In this design we propound optimized BCD adders with the use of modified DR gate. The main moto of designing reversible gate is to low the cost of design so that we get required output and to decrease quantum cost, gate count, no. of delays. The main aim for designing this is to refunctioned the actual parameters and results in flexibility. This architecture has been stimulated in VHDL technology using tool as Xilinx ISE 14.7 and then it can executed in FPGA.
Keywords
DR Gate, Nanotechnology, Optical Computing, Reversible Logic.
References
- C. H. Bennet, "Logical reversibility of computation", IBM 1. Res. Develop., vol. 17, no. 6, pp. 525-532,1973.
- R. Landauer, ‘‘Irreversibility and heat generation in the computational process’’, IBM J. Res. Develop., vol. 5, pp. 183-191, 1961.
- Nagamani A N, Ashwin S, Vinod Kumar Agarwal, ”Design of Optimised Reversible Binary Adder/Subtractorand BCD Adder”, International Conference on Contemporary computing and Informatics”, 978-1-4799-6629-5/14/$31.00 IEEE,pp-774-779
- H.G. Rangaraju, U. Venugopal , “Low power reversible parallel binary adder/subtractor,” International Journal of VLSI Design & Communication Systems, pp-23-34, arXiv: 1009.6218, 2010.
- Md. Saiful Islam, Md. Rafiqul Islam,Muhammad Rezaul Karim, Abdullah AlMahmud and Hafiz Md. Hasan Babu,“Variable Block Carry Skip Logic using Reversible Gates”, In Proc. of 10th International Symposium on Integrated Circuits, Devices & Systems, ISIC 2004, Nanyang Technological University, Suntec, Singapore, 8-10 September, 2004, pp 9-12.
- Md. Saiful Islam & Md. Rafiqul Islam, "Minimization of Reversible Adder Circuits", Asian Journal of Information Technology, Vol. 4, No. 12, pp. 1146-1151, 2005.
- S. Archana, G. Durga, “Design of Low Power and High Speed Ripple Carry Adder” International Conference on Communication and Signal Processing, April 3-5, 2014.
- Padhirtha Divya, Ganga Rames Jakkamsetthi, ”Design of 1-Bit ALU using Modified DR Gate”, Internation Journal of VLSI System Design and Communication System, ISSN 2322-0929, Vol.04, Issue.01, January-2016, Pages:0077-0081
- Harpreet Singh, Chakshu Goel,”Design of a Power Efficient Reversible Adder/Subtractor”,International Journal of Advanced Research in Computer Engineering and Technology, ISSN:2278-1323, vol-4, Issue-4, April 2015, pp1305-1308.
- Dipankar Saha, Subhramita Basak, Sagar Mukherjee, C.K.Sarkar, “A LowVoltage, Low-Power 4-bit BCD Adder, Designed Using the Clock Gated Power Gating, and the DVT Scheme ”IEEE,2013.
- V Kammalakannan, Shilpakala V, Ravi H N,”Design of Adder/Subtractorcircuit Based on Reversible gates”, International Journal of Advanced Research in Electrical, Electronic and Instrumentation Engineering”, ISSN: 2278-8875, vol 2, Issue 2, August 2013, pp-3796-3804.
- Thapliyal H., S. Kotiyal, M. B. Srinivas, 2006.Novel BCD adders & their reversible logic implementation for IEEE 754r format. Proceedings of the 19th International Conference on VLSI Design, 3 7 Jan 2006.
- Tilak B.G, Rashmi S.B & Praveen B“A Novel Optimized Reversible BCD Adder using reversible CL gate”, Proceedings of the 3rd International Conference on Computer Modelling and Simulations, ICCMS, jan 7-9, 2011.
- Polian & Hayes, "Advanced Modeling of Faults in Reversible Circuits", IEEE 978-1-4244-9556-6/10 2010
- Abhinash Kumar Pala, Jagmohan Das, ”Efficient Design of 4 bit Binary Adder Using Reversible Logic Gate”, International Journal of Engineering Science and Research Technology, ISSN:2277-9655, Vol 3, Issue 11, Nov 2014, PP-206-209.
- B. Parhami, "Fault tolerant reversible circuits", in Proceedings of 4(jhAsimolar Con! Signals, Systems, and Computers, Pacific Grove, CA, pp. 1726-1729, October 2006.
- Eleonora, Kamalika, Wille, Sengupta, & Rahaman, Rolf, "Optimizing DDbased Synthesis of Reversible Circuits using Negative Control lines", IEEE, 978-1- 4799-4558-0/14,2014
- Wille, Soeken, Nils, Rolf: "Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines",IEEE 42nd International Symposium on Multiple Valued Logic, 2012.
- Madhusmita Mahapatro, Sisira Kanta Panda, Jagannath Satpathy, Meraj Saheel, M.Suresh, Dr. Ajit Kumar Panda & M K Sukla, “Design of Arithmetic Circuits Using Reversible Logic Gates & Power Dissipation Calculation”, International Symposium on Electronic System Design, 2010.
- A.Anjana, “Design of RS flip flop using reversible logic gate”, IPASJ International Journal of Electronics & Communication (IIJEC), Volume 2, Issue 4, April 2014, pp 6-8.
- Pallav Gupta, Abhinav Agarwal, & Niraj K.Jha “An Algorithm for Synthesis of Reversible Logic Circuits”, IEEE transactions on computer Aided Design of Integrated circuits and Systems, vol.25, 2006.
- S.Archana, G.Durga, “Design of Low Power & High Speed Ripple Carry Adder” International Conference on Communication and Signal Processing, April 3-5, 2014.
- Jatinder Kumar, “Design and Comparative Analysis of CMOS Full Adder Cells Using Tanner EDA Tool” International Journal of Computer Science & Engineering Technology, February, 2014.
- Sanjeev Kumar, Pankaj Yadav, “Design of Six Transistor Full Adder Cell for VLSI Applications, International Journal of Research in Computer Applications and Robotics, November, 2013.
- Design of Low Power 4 Bit Carry Select Adder Using 14T Transistor 1 Bit Adder
Abstract Views :169 |
PDF Views:4
Authors
Affiliations
1 Department of Electronics and Telecommunication, Bhilai (C.G.), IN
2 Department of E & I, SSTC-SSGI, IN
1 Department of Electronics and Telecommunication, Bhilai (C.G.), IN
2 Department of E & I, SSTC-SSGI, IN
Source
Programmable Device Circuits and Systems, Vol 9, No 9 (2017), Pagination: 185-188Abstract
In the digital electronic, the adder are most important fundamental in wide variety of digital system. There are among the fast adder exist, but fast adding using less area, delay and power consumption is still challenging of digital electronic. The designer of integrated circuit, are occupancy play most important role because its increasing the necessary of portable system. The carry select adder is one of the fastest adders used in many data processing processors to perform fast arithmetic function. The carry select structure is required large area and more power consumption because its internal structure is consist of two ripple carry adder and the multiplexer. The moderns design of carry select adder requiring a reduction area and less power consumption. In this project, the proposed design using 14Ttransistor 1bit adder is used to design of 4 bit carry select adder has reduced the transistor count and providelesser power consumption as well as power delay product as compared to the other existing logic. The main advantage of proposed design of 4bit carry select adder using 14-T transistor 1bit adder provide lesser power consumption and power delay product. The simulation result is carried out using mentor graphic tanner EDA 16.3 version tool and BISM4 45nm CMOS technology.Keywords
Carry Select Adder, Low Power Design, 14T Transistor 1 Bit Adder, Nanometre Technology.References
- Padma Devi and Ashima Girdhar “Improved the Carry Select Adder with Reduced Area and Power Consumption”, International Journals of Computer Application, (IJCA) ISSN: 0975-8887, Vol-3, No-4, pp. 1418, June 2010.
- Samiappa Sakthikumaran, V.S Kanchana Bhaaskaran, B.Brindha, C.Vinoth, V.Kavinilava “A very fast low power carry select adder circuit” IEEE 3rd International Conferences on Electronic Computer Technology, Vol-1, DOI: 10.1109/ ICECTECH.20115941604, 2011.
- B.Ramkumar and Harish M Kittur, P.Mahesh Kannan “ASIC Implementation of Modified Faster Carry Save Adder”, European Journal of Scientific Research ISSN 1450-216X Vol.42 No.1, pp.53-58, 2010.
- V.Sajesh Kumar, K.K Mohamed Salih, K.Sajith “Design and Implementation of Carry Select Adder without using Multiplexer” 1st International Conferences on Emerging Technology Trends in Electronic, Communication and Networking, DOI:10.1109/et2ecn.2012.6470067,2012.
- B. Ramkumar and H. M. Kittur, “Low-power and area-efficient carry select adder”, IEEE Transaction on Very Large Scale Integration Systems, vol. 20, no. 2, pp. 371–375,feb 2012.
- Laxman Shanigarapu, Bhavana P. Shrivastava “Low-Power and High Speed Carry Select Adder”, International Journal of Scientific and Research Publications, Volume. 3, Issue 8, ISSN: 2250-3153, Aug.2013.
- A.P Thakare, S.Agrawal “Design of High Efficiency Carry Select Adder using SQRT Technique” International Journal Emerging Technology and Advanced Engineering, vol.3, Issue 7, ISSN:2250-2459,ISO:9001:2008,July-2013.
- Damarla Paradhasaradhi, Anusudha. K “An Area Efficient Enhanced SQRT Carry Select Adder”, International. Journal of Engineering Research and Applications ISSN: 2248-9622, Volume. 3, Issue 6, pp.876-880, Nov-Dec-2013.
- Yan Sun, Xin Zhang, Jin Xi, ”High Performances Carry Select Adder using Fast All One Finding Logic” IEEE International Conferences on Computer Technology DOI:10.1109/AMS.2008.90,2008
- Pallavi Saxena, Urvashi Purohit,Priyanka Joshi “Proposed Modified Carry select Adder is using single RCA and BEC instead of dual RCA in order to reduce the area and power consumption” International Journal of Engineering Research and Technology (IJERT) ISSN:2278-0181,vol.2 Issue 10,Oct.-2013.
- L. Mugilvannan and S. Ramasamy, “Low-power and area-efficient carry select adder using modified BEC-1 converter” International Journal of Computer Application in Engineering Science (IJCASE),Vol.3, Special Issue on National conference on Information and communications, pp. 1-5, July 2013.
- Gagandeep Singh and Chakshu Goel “Design of low power and efficient carry select adder using 3-T-XOR gate” Research Article of Hindawi Publishing Corporation of Advance Electronic, vol 2014, article id 564513, June-2014.
- Basant Kumar Mohanty, Sujit Kumar Patel, “Area–Delay–Power Efficient Carry-Select Adder” IEEE Transactions On Circuits and Systems, Vol. 61, No. 6, June 2014.
- J. Eric Clapten, E. Konguvel and M. Thangamani, “VLSI implementation of low power area efficient fast Carry Select Adder” International Journal of Computer Applications, Vol. 115, No.6, pp. 5-8, April 2015.
- Rishabh Rai, Rajni Parashan, “Low Power and Area Efficient Carry Select Adder” International Journal of Scientific Research and Development (IJSRD) Vol-3, Issue-4, ISSN-2321- 0613, 2015.